TY  - JOUR
A1  - Geiger, Michael
A1  - Acharya, Rachana
A1  - Reutter, Eric
A1  - Ferschke, Thomas
A1  - Zschieschang, Ute
A1  - Weis, Jürgen
A1  - Pflaum, Jens
A1  - Klauk, Hagen
A1  - Weitz, Ralf Thomas
T1  - Effect of the Degree of the Gate‐Dielectric Surface Roughness on the Performance of Bottom‐Gate Organic Thin‐Film Transistors
JF  - Advanced Materials Interfaces
N2  - In organic thin‐film transistors (TFTs) fabricated in the inverted (bottom‐gate) device structure, the surface roughness of the gate dielectric onto which the organic‐semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics. To quantitatively evaluate this effect, a method to tune the surface roughness of a gate dielectric consisting of a thin layer of aluminum oxide and an alkylphosphonic acid self‐assembled monolayer over a wide range by controlling a single process parameter, namely the substrate temperature during the deposition of the aluminum gate electrodes, is developed. All other process parameters remain constant in the experiments, so that any differences observed in the TFT performance can be confidently ascribed to effects related to the difference in the gate‐dielectric surface roughness. It is found that an increase in surface roughness leads to a significant decrease in the effective charge‐carrier mobility and an increase in the subthreshold swing. It is shown that a larger gate‐dielectric surface roughness leads to a larger density of grain boundaries in the semiconductor layer, which in turn produces a larger density of localized trap states in the semiconductor.
KW  - grain boundaries
KW  - organic thin‐film transistors
KW  - surface roughness
Y1  - 2020
U6  - http://nbn-resolving.de/urn/resolver.pl?urn:nbn:de:bvb:20-opus-214830
VL  - 7
IS  - 10
ER  -