@phdthesis{Runge2017,
  author    = {Runge, Armin},
  title     = {Advances in Deflection Routing based Network on Chips},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-149700},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2017},
  abstract  = {The progress which has been made in semiconductor chip production in recent years enables a multitude of cores on a single die. However, due to further decreasing structure sizes, fault tolerance and energy consumption will represent key challenges. Furthermore, an efficient communication infrastructure is indispensable due to the high parallelism at those systems. The predominant communication system at such highly parallel systems is a Network on Chip (NoC). The focus of this thesis is on NoCs which are based on deflection routing. In this context, contributions are made to two domains, fault tolerance and dimensioning of the optimal link width. Both aspects are essential for the application of reliable, energy efficient, and deflection routing based NoCs. It is expected that future semiconductor systems have to cope with high fault probabilities. The inherently given high connectivity of most NoC topologies can be exploited to tolerate the breakdown of links and other components. In this thesis, a fault-tolerant router architecture has been developed, which stands out for the deployed interconnection architecture and the method to overcome complex fault situations. The presented simulation results show, all data packets arrive at their destination, even at high fault probabilities. In contrast to routing table based architectures, the hardware costs of the herein presented architecture are lower and, in particular, independent of the number of components in the network. Besides fault tolerance, hardware costs and energy efficiency are of great importance. The utilized link width has a decisive influence on these aspects. In particular, at deflection routing based NoCs, over- and under-sizing of the link width leads to unnecessary high hardware costs and bad performance, respectively. In the second part of this thesis, the optimal link width at deflection routing based NoCs is investigated. Additionally, a method to reduce the link width is introduced. Simulation and synthesis results show, the herein presented method allows a significant reduction of hardware costs at comparable performance.},
  subject      = {Network-on-Chip},
  language  = {en}
}
@phdthesis{Bregenzer2015,
  author    = {Bregenzer, J{\"u}rgen},
  title     = {Effizienter Einsatz von Multicore-Architekturen in der Steuerungstechnik},
  publisher = {W{\"u}rzburg University Press},
  address   = {W{\"u}rzburg},
  isbn      = {978-3-95826-010-8 (Print)},
  doi       = {10.25972/WUP-978-3-95826-011-5},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-106239},
  school      = {W{\"u}rzburg University Press},
  pages     = {185},
  year      = {2015},
  abstract  = {Der Einsatz von Multicore-Prozessoren in der industriellen Steuerungstechnik birgt sowohl Chancen als auch Risiken. Die vorliegende Dissertation entwickelt und bewertet aus diesem Grund generische Strategien zur Nutzung dieser Prozessorarchitektur unter Ber{\"u}cksichtigung der spezifischen Rahmenbedingungen und Anforderungen dieser Dom{\"a}ne. Multicore-Prozessoren bieten die Chance zur Konsolidierung derzeit auf dedizierter Hardware ausgef{\"u}hrter heterogener Steuerungssubsysteme unter einer bisher nicht erreichbaren temporalen Isolation. In diesem Kontext definiert die vorliegende Dissertation die spezifischen Anforderungen, die eine integrierte Ausf{\"u}hrung in der Dom{\"a}ne der industriellen Automatisierung erf{\"u}llen muss. Eine Vorbedingung f{\"u}r ein derartiges Szenario stellt allerdings der Einsatz einer geeigneten Konsolidierungsl{\"o}sung dar. Mit einem virtualisierten und einem hybriden Konsolidierungsansatz werden deshalb zwei repr{\"a}sentative L{\"o}sungen f{\"u}r die Dom{\"a}ne eingebetteter Systeme vorgestellt, die schließlich hinsichtlich der zuvor definierten Kriterien evaluiert werden. Da die Taktraten von Prozessoren physikalische Grenzen erreicht haben, werden sich in der Steuerungstechnik signifikante Performanzsteigerungen zuk{\"u}nftig nur durch den Einsatz von Multicore-Prozessoren erzielen lassen. Dies hat zur Vorbedingung, dass die Firmware die Parallelit{\"a}t dieser Prozessorarchitektur in geeigneter Weise zu nutzen vermag. Leider entstehen bei der Parallelisierung eines komplexen Systems wie einer Automatisierungs-Firmware im Allgemeinen signifikante Aufw{\"a}nde. Infolgedessen sollten diesbez{\"u}gliche Entscheidungen nur auf Basis einer objektiven Abw{\"a}gung potentieller Alternativen getroffen werden. Allerdings macht die Systemkomplexit{\"a}t eine Absch{\"a}tzung der durch eine spezifische parallele Firmware-Architektur zu erwartenden Performanz zu einer anspruchsvollen Aufgabe. Dies gilt vor allem, da eine Parallelisierung gefordert wird, die f{\"u}r eine Vielzahl von Lastszenarien in Form gesteuerter Maschinen geeignet ist. Aus diesem Grund spezifiziert die vorliegende Dissertation eine anwendungsorientierte Methode zur Unterst{\"u}tzung von Entwurfsentscheidungen, die bei der Migration einer bestehenden Singlecore-Firmware auf eine homogene Multicore-Architektur zu treffen sind. Dies wird erreicht, indem in automatisierter Weise geeignete Firmware-Modelle auf Basis von dynamischem Profiling der Firmware unter mehreren repr{\"a}sentativen Lastszenarien erstellt werden. Im Anschluss daran werden diese Modelle um das Expertenwissen von Firmware-Entwicklern erweitert, bevor mittels multikriterieller genetischer Algorithmen der Entwurfsraum der Parallelisierungsalternativen exploriert wird. Schließlich kann eine spezifische L{\"o}sung der auf diese Weise hergeleiteten Pareto-Front auf Basis ihrer Bewertungsmetriken zur Implementierung durch einen Entwickler ausgew{\"a}hlt werden. Die vorliegende Arbeit schließt mit einer Fallstudie, welche die zuvor beschriebene Methode auf eine numerische Steuerungs-Firmware anwendet und dabei deren Potential f{\"u}r eine umfassende Unterst{\"u}tzung einer Firmware-Parallelisierung aufzeigt.},
  subject      = {Mehrkernprozessor},
  language  = {de}
}
@phdthesis{Flederer2021,
  author    = {Flederer, Frank},
  title     = {CORFU - An Extended Model-Driven Framework for Small Satellite Software with Code Feedback},
  doi       = {10.25972/OPUS-24981},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-249817},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2021},
  abstract  = {Corfu is a framework for satellite software, not only for the onboard part but also for the ground. Developing software with Corfu follows an iterative model-driven approach. The basis of the process is an engineering model. Engineers formally describe the basic structure of the onboard software in configuration files, which build the engineering model. In the first step, Corfu verifies the model at different levels. Not only syntactically and semantically but also on a higher level such as the scheduling. Based on the model, Corfu generates a software scaffold, which follows an application-centric approach. Software images onboard consist of a list of applications connected through communication channels called topics. Corfu's generic and generated code covers this fundamental communication, telecommand, and telemetry handling. All users have to do is inheriting from a generated class and implement the behavior in overridden methods. For each application, the generator creates an abstract class with pure virtual methods. Those methods are callback functions, e.g., for handling telecommands or executing code in threads. However, from the model, one can not foresee the software implementation by users. Therefore, as an innovation compared to other frameworks, Corfu introduces feedback from the user code back to the model. In this way, we extend the engineering model with information about functions/methods, their invocations, their stack usage, and information about events and telemetry emission. Indeed, it would be possible to add further information extraction for additional use cases. We extract the information in two ways: assembly and source code analysis. The assembly analysis collects information about the stack usage of functions and methods. On the one side, Corfu uses the gathered information to accomplished additional verification steps, e.g., checking if stack usages exceed stack sizes of threads. On the other side, we use the gathered information to improve the performance of onboard software. In a use case, we show how the compiled binary and bandwidth towards the ground is reducible by exploiting source code information at run-time.},
  subject      = {FRAMEWORK <Programm>},
  language  = {en}
}
@phdthesis{Appold2015,
  author    = {Appold, Christian},
  title     = {Symbolische BDD-basierte Modellpr{\"u}fung asynchroner nebenl{\"a}ufiger Systeme},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-137029},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2015},
  abstract  = {Today, information and communication systems are ubiquitous and consist very often of several interacting and communicating components. One reason is the widespread use of multi-core processors and the increasing amount of concurrent software for the efficient usage of multi-core processors. Also, the dissemination of distributed emergent technologies like sensor networks or the internet of things is growing. Additionally, a lot of internet protocols are client-server architectures with clients which execute computations in parallel and servers that can handle requests of several clients in parallel. Systems which consist of several interacting and communicating components are often very complex and due to their complexity also prone to errors. Errors in systems can have dramatic consequenses, especially in safety-critical areas where human life can be endangered by incorrect system behavior. Hence, it is inevitable to have methods that ensure the proper functioning of such systems. This thesis aims on improving the verifiability of asynchronous concurrent systems using symbolic model checking based on Binary Decision Diagrams (BDDs). An asynchronous concurrent system is a system that consists of several components, from which only one component can execute a transition at a time. Model checking is a formal verification technique. For a given system description and a set of desired properties, the validity of the properties for the system is decided in model checking automatically by software tools called model checkers. The main problem of model checking is the state-space explosion problem. One approach to reduce this problem is the use of symbolic model checking. There, system states and transitions are not stored explicitely as in explicit model checking. Instead, in symbolic model checking sets of states and sets of transitions are stored and also manipulated together. The data structure which is used in this thesis to store those sets are BDDs. BDD-based symbolic model checking has already been used successful in industry for several times. Nevertheless, BDD-based symbolic model checking still suffers from the state-space explosion problem and further improvements are necessary to improve its applicability. Central operations in BDD-based symbolic model checking are the computation of successor and predecessor states of a given set of states. Those computations are called image computations. They are applied repeatedly in BDD-based symbolic model checking to decide the validity of properties for a given system description. Hence, their efficient execution is crucial for the memory and runtime requirements of a model checker. In an image computation a BDD for a set of transitions and a BDD for a set of states are combined to compute a set of successor or predecessor states. Often, also the size of the BDDs to represent the transition relation is critical for the successful use of model checking. To further improve the applicability of symbolic model checking, we present in this thesis new data structures to store the transition relation of asynchronous concurrent systems. Additionally, we present new image computation algorithms. Both can lead to large runtime and memory reductions for BDD-based symbolic model checking. Asynchronous concurrent systems often contain symmetries. A technique to exploit those symmetries to diminish the state-space explosion problem is symmetry reduction. In this thesis we also present a new efficient algorithm for symmetry reduction in BDD-based symbolic model checking.},
  subject      = {Programmverifikation},
  language  = {de}
}
@phdthesis{Gageik2015,
  author    = {Gageik, Nils},
  title     = {Autonome Quadrokopter zur Innenraumerkundung : AQopterI8, Forschung und Entwicklung},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-130240},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2015},
  abstract  = {Diese Forschungsarbeit beschreibt alle Aspekte der Entwicklung eines neuartigen, autonomen Quadrokopters, genannt AQopterI8, zur Innenraumerkundung. Dank seiner einzigartigen modularen Komposition von Soft- und Hardware ist der AQopterI8 in der Lage auch unter widrigen Umweltbedingungen autonom zu agieren und unterschiedliche Anforderungen zu erf{\"u}llen. Die Arbeit behandelt sowohl theoretische Fragestellungen unter dem Schwerpunkt der einfachen Realisierbarkeit als auch Aspekte der praktischen Umsetzung, womit sie Themen aus den Gebieten Signalverarbeitung, Regelungstechnik, Elektrotechnik, Modellbau, Robotik und Informatik behandelt. Kernaspekt der Arbeit sind L{\"o}sungen zur Autonomie, Hinderniserkennung und Kollisionsvermeidung. Das System verwendet IMUs (Inertial Measurement Unit, inertiale Messeinheit) zur Orientierungsbestimmung und Lageregelung und kann unterschiedliche Sensormodelle automatisch detektieren. Ultraschall-, Infrarot- und Luftdrucksensoren in Kombination mit der IMU werden zur H{\"o}henbestimmung und H{\"o}henregelung eingesetzt. Dar{\"u}ber hinaus werden bildgebende Sensoren (Videokamera, PMD), ein Laser-Scanner sowie Ultraschall- und Infrarotsensoren zur Hindernis-erkennung und Kollisionsvermeidung (Abstandsregelung) verwendet. Mit Hilfe optischer Sensoren kann der Quadrokopter basierend auf Prinzipien der Bildverarbeitung Objekte erkennen sowie seine Position im Raum bestimmen. Die genannten Subsysteme im Zusammenspiel erlauben es dem AQopterI8 ein Objekt in einem unbekannten Raum autonom, d.h. v{\"o}llig ohne jedes externe Hilfsmittel, zu suchen und dessen Position auf einer Karte anzugeben. Das System kann Kollisionen mit W{\"a}nden vermeiden und Personen autonom ausweichen. Dabei verwendet der AQopterI8 Hardware, die deutlich g{\"u}nstiger und Dank der Redundanz gleichzeitig erheblich verl{\"a}sslicher ist als vergleichbare Mono-Sensor-Systeme (z.B. Kamera- oder Laser-Scanner-basierte Systeme). Neben dem Zweck als Forschungsarbeit (Dissertation) dient die vorliegende Arbeit auch als Dokumentation des Gesamtprojektes AQopterI8, dessen Ziel die Erforschung und Entwicklung neuartiger autonomer Quadrokopter zur Innenraumerkundung ist. Dar{\"u}ber hinaus wird das System zum Zweck der Lehre und Forschung an der Universit{\"a}t W{\"u}rzburg, der Fachhochschule Brandenburg sowie der Fachhochschule W{\"u}rzburg-Schweinfurt eingesetzt. Darunter fallen Labor{\"u}bungen und 31 vom Autor dieser Arbeit betreute studentische Bachelor- und Masterarbeiten. Das Projekt wurde ausgezeichnet vom Universit{\"a}tsbund und der IHK W{\"u}rzburg-Mainfranken mit dem Universit{\"a}tsf{\"o}rderpreis der Mainfr{\"a}nkischen Wirtschaft und wird gef{\"o}rdert unter den Bezeichnungen „Lebensretter mit Propellern" und „Rettungshelfer mit Propellern". Außerdem wurde die Arbeit f{\"u}r den Gips-Sch{\"u}le-Preis nominiert. Absicht dieser Projekte ist die Entwicklung einer Rettungsdrohne. In den Medien Zeitung, Fernsehen und Radio wurde {\"u}ber den AQopterI8 schon mehrfach berichtet. Die Evaluierung zeigt, dass das System in der Lage ist, voll autonom in Innenr{\"a}umen zu fliegen, Kollisionen mit Objekten zu vermeiden (Abstandsregelung), eine Suche durchzuf{\"u}hren, Objekte zu erkennen, zu lokalisieren und zu z{\"a}hlen. Da nur wenige Forschungsarbeiten diesen Grad an Autonomie erreichen, gleichzeitig aber keine Arbeit die gestellten Anforderungen vergleichbar erf{\"u}llt, erweitert die Arbeit den Stand der Forschung.},
  subject      = {Quadrokopter},
  language  = {de}
}
@phdthesis{Muehlberger2018,
  author    = {M{\"u}hlberger, Clemens},
  title     = {Design of a Self-Organizing MAC Protocol for Dynamic Multi-Hop Topologies},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-158788},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2018},
  abstract  = {Biologically inspired self-organization methods can help to manage the access control to the shared communication medium of Wireless Sensor Networks. One lightweight approach is the primitive of desynchronization, which relies on the periodic transmission of short control messages - similar to the periodical pulses of oscillators. This primitive of desynchronization has already been successfully implemented as MAC protocol for single-hop topologies. Moreover, there are also some concepts of such a protocol formulti-hop topologies available. However, the existing implementations may handle just a certain class of multi-hop topologies or are not robust against topology dynamics. In addition to the sophisticated access control of the sensor nodes of a Wireless Sensor Network in arbitrary multi-hop topologies, the communication protocol has to be lightweight, applicable, and scalable. These characteristics are of particular interest for distributed and randomly deployed networks (e.g., by dropping nodes off an airplane). In this work we present the development of a self-organizing MAC protocol for dynamic multi-hop topologies. This implies the evaluation of related work, the conception of our new communication protocol based on the primitive of desynchronization as well as its implementation for sensor nodes. As a matter of course, we also analyze our realization with regard to our specific requirements. This analysis is based on several (simulative as well as real-world) scenarios. Since we are mainly interested in the convergence behavior of our protocol, we do not focus on the "classical" network issues, like routing behavior or data rate, within this work. Nevertheless, for this purpose we make use of several real-world testbeds, but also of our self-developed simulation framework. According to the results of our evaluation phase, our self-organizing MAC protocol for WSNs, which is based on the primitive of desynchronization, meets all our demands. In fact, our communication protocol operates in arbitrary multi-hop topologies and copes well with topology dynamics. In this regard, our protocol is the first and only MAC protocol to the best of our knowledge. Moreover, due to its periodic transmission scheme, it may be an appropriate starting base for additional network services, like time synchronization or routing.},
  language  = {en}
}
@phdthesis{Runge2022,
  author    = {Runge, Isabel Madeleine},
  title     = {Network Coding for Reliable Data Dissemination in Wireless Sensor Networks},
  doi       = {10.25972/OPUS-27224},
  url       = {http://nbn-resolving.de/urn:nbn:de:bvb:20-opus-272245},
  school      = {Universit{\"a}t W{\"u}rzburg},
  year      = {2022},
  abstract  = {The application of Wireless Sensor Networks (WSNs) with a large number of tiny, cost-efficient, battery-powered sensor nodes that are able to communicate directly with each other poses many challenges. Due to the large number of communicating objects and despite a used CSMA/CA MAC protocol, there may be many signal collisions. In addition, WSNs frequently operate under harsh conditions and nodes are often prone to failure, for example, due to a depleted battery or unreliable components. Thus, nodes or even large parts of the network can fail. These aspects lead to reliable data dissemination and data storage being a key issue. Therefore, these issues are addressed herein while keeping latency low, throughput high, and energy consumption reduced. Furthermore, simplicity as well as robustness to changes in conditions are essential here. In order to achieve these aims, a certain amount of redundancy has to be included. This can be realized, for example, by using network coding. Existing approaches, however, often only perform well under certain conditions or for a specific scenario, have to perform a time-consuming initialization, require complex calculations, or do not provide the possibility of early decoding. Therefore, we developed a network coding procedure called Broadcast Growth Codes (BCGC) for reliable data dissemination, which performs well under a broad range of diverse conditions. These can be a high probability of signal collisions, any degree of nodes' mobility, a large number of nodes, or occurring node failures, for example. BCGC do not require complex initialization and only use simple XOR operations for encoding and decoding. Furthermore, decoding can be started as soon as a first packet/codeword has been received. Evaluations by using an in-house implemented network simulator as well as a real-world testbed showed that BCGC enhance reliability and enable to retrieve data dependably despite an unreliable network. In terms of latency, throughput, and energy consumption, depending on the conditions and the procedure being compared, BCGC can achieve the same performance or even outperform existing procedures significantly while being robust to changes in conditions and allowing low complexity of the nodes as well as early decoding.},
  subject      = {Zuverl{\"a}ssigkeit},
  language  = {en}
}